Prediction of Intermittent Failure by Presage Debacle Model in Network on Chip

With the emergence of deep sub-micron technology, reliability issues in on-chip interconnect has enormously increased. This includes single event upsets, like soft errors, and hard faults which are rapidly becoming important factors to be considered. Aggressive technology scaling renders these architectures vulnerable system performance, intermittent failure, capacitive crosstalk, power dissipation problem. To improve performance area consumption along with bandwidth, throughput latency, a Buffer Potency Power Gating Technique is carried out predict Intermittent Failure by Presage Debacle Model Network on Chip. In Model, links present application-specific topology provided real application traffic assist prediction failure. By predicting output model provides dissipated over connection link. Then crosstalk noise reduced Adaption Simulated Annealing (SA) based Particle Swarm Optimization (PSO) congruence algorithm. The optimization algorithm assigns each task software node determine network's optimal output. It continuously changes park position reduces NoC. Consecutively, minimized Technique. efficiency increased power-gating practical way mitigate NoC control schemes properly effectively without any loss performance. Thus failure obtained utilizing consumption.